Method for separating regions of a semiconductor layer

ABSTRACT

The invention relates to a method for separating regions of a semiconductor layer and for introducing an outcoupling structure into an upper side of the semiconductor layer, the outcoupling structure being provided to couple light out of the semiconductor layer. The upper side of the semiconductor layer is covered by a mask having first openings for introducing the outcoupling structure and at least a second opening, which is provided to introduce a separating trench into the semiconductor layer. With the aid of an etching method, the outcoupling structure is introduced into the upper side of the semiconductor layer in the region of the first openings and simultaneously a separating trench passing through the semiconductor layer is introduced into the semiconductor layer via the second opening, and a region of the semiconductor layer is separated.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.14/430,872, filed Mar. 24, 2015, now U.S. Pat. No. 9,589,943 issued Mar.7, 2017, which is a national stage application of International PatentApplication No. PCT/EP2013/070042, filed Sep. 26, 2013, which claims thebenefit of priority to German Patent Application No. 102012217524.5,filed on Sep. 27, 2012 and German Patent Application No. 102012220909.3,filed on Nov. 15, 2012, all of which are hereby incorporated byreference in their entirety for all purposes.

DESCRIPTION

The invention relates to a method for separating regions of asemiconductor layer according to patent claim 1 and to an optoelectronicsemiconductor chip according to claim 8.

DE 10 2011 010 503 A1 discloses providing a semiconductor layer of anoptoelectronic semiconductor chip with a mask and introducing acoupling-out structure into a coupling-out side of the semiconductorlayer. Afterward, the mask is removed and, with the aid of a secondmask, likewise by means of an etching method, the semiconductor layer isseparated into individual regions from which individual semiconductorchips are produced later.

The object of the invention is to provide a simpler and faster methodfor separating regions of a semiconductor layer and for introducing acoupling-out structure into the semiconductor layer.

The object is achieved by means of the method according to claim 1 andthe semiconductor chip according to claim 10. Further advantageousembodiments are specified in the dependent claims.

The method described has the advantage that, just with one mask and inone method step, the coupling-out structure is introduced into thesemiconductor layer and at the same time at least one region of thesemiconductor layer is separated. Consequently, the method described issimple, cost-effective and fast to carry out. In contrast to the priorart, it is not necessary to use a plurality of masks and/or to carry outa plurality of etching methods. By way of example, an optoelectronicsemiconductor chip having a semiconductor layer for generating light isproduced with the aid of the method described. As a result of thesimultaneous roughening and the introduction of a trench around thesemiconductor chip, i.e. the mesa etching, a non-roughened edge isobtained around the semiconductor chip. On account of this sharp chipedge, the chip edge can be monitored more easily for defects orcontaminants in a concluding optical inspection. The reliability of theoptical inspection is increased as a result.

In the prior art, the chip edge is also roughened and, as a result, thechip edge appears very wavy in the inspection, such that a cleardefinable boundary for the automatic inspection can be recognized onlywith difficulty.

In one embodiment, the mask is applied in one method step and thus has auniform thickness.

In one development, a hard mask is used as the mask. The hard mask issimple to produce, cost-effective and enables an accurate structuring ofthe coupling-out structure and of the separation of a region of thesemiconductor layer.

In a further embodiment, the hard mask is a resist mask.

In a further embodiment, a gaseous or liquid etching medium is used asetchant. The use of gaseous or liquid etching media constitutes a knowntechnology and enables the method to be carried out cost-effectively.

In a further embodiment, the etching method is a dry etching method.

In a further embodiment, a plasma is used in the dry etching method. Byway of example, this involves a Cl plasma.

The method described is particularly suitable for introducing acoupling-out structure into an epitaxially applied semiconductor layer.By way of example, the epitaxially grown semiconductor layer can beembodied in the form of a gallium nitride layer.

In a further embodiment, after the removal of the mask, a furtherstructuring step is carried out in order to provide the previouslycovered regions of the semiconductor layer with a coupling-outstructure. The efficiency for coupling out light is improved in thisway.

The above-described properties, features and advantages of thisinvention and the way in which they are achieved will become clearer andmore clearly understood in association with the following description ofthe exemplary embodiments which are explained in greater detail inassociation with the drawings, wherein

FIG. 1 shows a first method step in a schematic illustration,

FIG. 2 shows a second method step in a schematic illustration,

FIG. 3 shows a schematic plan view of a semiconductor layer with a mask,and

FIG. 4 shows a schematic illustration of semiconductor chips.

FIG. 1 shows a schematic sectional view of a semiconductor layer 2, onthe top side of which a structured mask 1 is applied. The semiconductorlayer 2 can be arranged on a carrier 20, as illustrated. The carrier 20can for example comprise Ge, Si, GaAs, AlN or SiN or consist of acorresponding layer composed of Ge, Si, GaAs, AlN or SiN. The mask 1 isembodied in the form of a hard mask for example. The hard mask cancomprise silicon nitride or silicon oxide, for example. Furthermore, thehard mask can also be a resist mask. The structuring of the mask isperformed by means of a lithographic method using photoresist andcorresponding etching media. By way of example, an etching process usinghydrofluoric acid (HF) or an ammonia-buffered hydrofluoric acid can becarried out for structuring or for removing the mask.

The semiconductor layer 2 comprises an upper first doped semiconductorlayer 3, for example. Adjoining the first semiconductor layer 3, asecond doped semiconductor layer 4 is provided. The first semiconductorlayer 3 can be negatively doped and the second semiconductor layer 4 canbe positively doped. Equally, the first semiconductor layer 3 can bepositively doped and the second semiconductor layer 4 can be negativelydoped. An active zone 5 for generating light is formed in the boundaryregion between the first and second semiconductor layers 3, 4. Morecomplex layer structures for the formation of an active zone 5 can alsobe provided depending on the embodiment chosen. In particular, theactive zone 5 can be formed from a sequence of layers having differentdopings. The semiconductor layer 2 constitutes for example anoptoelectronic semiconductor layer, in particular an LED semiconductorchip.

The structured mask 1 is applied on the first semiconductor layer 3.Depending on the embodiment chosen, the semiconductor layer 2 can alsocomprise other or additional layers, in particular a mirror layer.

The mask 1 has first mask elements 10 and second mask elements 12. Afirst opening 40 is in each case provided between a first mask element10 and a further first mask element 10, or between a first mask element10 and a second mask element 12. The width of the first opening 40, i.e.a first distance 13 between a first mask element 10 and a further firstmask element 10 or between a first mask element 10 and a second maskelement 12, is in a first range. By way of example, the first distances13 between two first mask elements 10 and a first mask element 10 and asecond mask element 12 are identical in magnitude. The second maskelement 12 is arranged in each case circumferentially around a region ofthe semiconductor layer 2. The second mask element 12 can have a widthof 10 μm to 5 μm, for example.

The first mask elements 10 preferably have the same width along anx-axis illustrated in FIG. 1. The width of the second mask element 12along the x-axis is greater than the width of the first mask elements 10along the x-axis. A second opening 41 is provided between two secondmask elements 12. The second opening 41 has a greater second width 14than the first opening 40 in the x-axis. Consequently, two adjacentsecond mask elements 12 have a greater second distance 14 than twoadjacent first mask elements 10. Moreover, two adjacent second maskelements 12 have a greater second distance 14 than a second mask element12 from a first mask element 10. The first distance 13 is thus less thanthe second distance 14. The first distance 13 is defined in such a waythat, during an etching process, a desired cutout is introduced into thesemiconductor layer 2, which constitutes a part of an opticalcoupling-out structure. The second distance 14 is chosen in such a waythat simultaneously during the etching process for introducing theoptical coupling-out structure a separating trench is introduced intothe semiconductor layer 2, said separating trench extending through theentire thickness of the semiconductor layer 2. The second distance canbe between 1.5 μm and 2.5 μm, for example. The magnitude of the seconddistance 14 depends on the thickness and the material of thesemiconductor layer 2 and on the etching method used, in particular onthe etching medium. The etching medium used can be for example KOH orphosphoric acid for a wet-chemical etching method.

FIG. 2 shows the arrangement from FIG. 1 after the etching process hasbeen carried out. Between two first mask elements 10 and between a firstmask element 10 and a second mask element 12, in each case a cutout 15is introduced into the semiconductor layer 2. Moreover, between twosecond mask elements 12, a separating trench 16 is introduced into thesemiconductor layer 2.

The cutouts 15 have boundary surfaces 17, 18 that support a coupling-outof light generated by the active zone 5. The separating trench 16extends over the entire thickness of the semiconductor layer 2. If theseparating trench 16 is embodied as a closed ring in the plane of thesemiconductor layer 2, then a first and a second region 19, 20 of thesemiconductor layer 2 are separated, as a result of the formation of theseparating trench 16 i.e. a mesa etching is carried out. A region of thesemiconductor layer 2 is separated by the separating trench 16, as aresult of which a semiconductor chip such as e.g. an LED chip isseparated. In the case where a carrier 20 is provided, the individualregions of the carrier 20 can be separated by a further etching methodand/or by a laser separating method along the separating trench 16. Anoptoelectronic semiconductor chip, in particular an LED having a regionof the semiconductor layer can be produced after the separation of theregions of the semiconductor layer.

The boundary surfaces 17, 18 arranged in an inclined manner reduce thatproportion of electromagnetic radiation which is subjected to totalinternal reflection at the outer surface of the layer 2. The boundarysurfaces 17, 18 form an angle of for example 35° to 75°, preferably 50°to 70°, with the plane of the layer 2. The concrete angle is predefinedby a crystal direction of the doped first semiconductor layer 3 and thechemical removal. The etching depth, i.e. the depth of the cutouts 15,can be in the micrometers range. The cutouts 15 can have pyramidaldepressions. In the case of an etching depth in the micrometers rangeand in the case of angles from above ranges of values, the cutouts 15have the shape of pyramids which are particularly suitable for couplingout electromagnetic radiation in the visible wavelength range, that isto say at wavelengths of between 0.3 μm and approximately 0.8 μm. Thediameter of a base of the pyramidal cutouts 15 is likewise in themicrometers range. The diameter is thus significantly greater than thewavelength of the electromagnetic radiation. The base of the pyramidalcutout has a hexagonal shape, in the case of the embodiment of the firstsemiconductor layer 3 composed of gallium nitride. After the removal ofthe mask 1, a plurality of separated semiconductor chips are obtained,wherein a central region of each semiconductor chip is roughened. Theroughened central region is surrounded by a smooth, non-roughened edgewhich was covered by the second mask element 12 during the etching.

In a further embodiment, the mask 1 is subsequently removed and the thenuncovered regions of the surface of the first semiconductor layer 3 areroughened by means of a further etching step. The regions covered in thefirst etching step are thus also provided with a coupling-out structure.

The semiconductor layer can be embodied as an epitaxially grown layerstructure having a plurality of layers. In this case, the individuallayers can consist of a III-V semiconductor material. By way of example,a layer of the semiconductor layer can be embodied on the basis of GaN,GaInN or AlN. Moreover, a layer can be constructed on the basis ofInGaAlN. InGaAlN-based layer structures include, in particular, those inwhich the epitaxially produced layer structure generally comprises alayer sequence composed of different individual layers which contains atleast one individual layer comprising a material from the III-V compoundsemiconductor material system InxAlyGa1-x-yN where 0<=x<=1, 0<=y<=1 andx+y<=1. The layer structure comprising at least one active layer or anactive region on the basis of InGaAlN can emit for exampleelectromagnetic radiation in an ultraviolet to green wavelength range.

Alternatively or additionally, the layers of the semiconductor layer canalso be based on InGaAlP, that is to say that the layer structure cancomprise different individual layers, at least one individual layer ofwhich comprises a material from the III-V compound semiconductormaterial system InxAlyGa1-x-yP where 0<=x<=1, 0<=y<=1 and x+y<=1. Thelayer structure comprising at least one active layer or an active regionon the basis of InGaAlP can for example preferably emit electromagneticradiation having one or more spectral components in a green to redwavelength range.

Alternatively or additionally, the layers of the semiconductor layer canalso comprise other III-V compound semiconductor material systems, forexample an AlGaAs-based material, or II-VI compound semiconductormaterial systems. In particular, an active layer comprising anAlGaAs-based material can be suitable for emitting electromagneticradiation having one or more spectral components in a red to infraredwavelength range. A II-VI compound semiconductor material system cancomprise at least one element from the second main group, such as Be,Mg, Ca, Sr, for example, and an element from the sixth main group, suchas O, S, Se, for example. In particular, a II-VI compound semiconductormaterial system comprises a binary, ternary or quaternary compoundcomprising at least one element from the second main group and at leastone element from the sixth main group. Such a binary, ternary orquaternary compound can moreover comprise for example one or a pluralityof dopants and additional constituents. By way of example, the II-VIcompound semiconductor materials include ZnSe, ZnTe, ZnO, ZnMgO, ZnS,CdS, ZnCdS, MgBeO.

FIG. 3 shows, in a schematic illustration, a plan view of asemiconductor layer 2 provided with a mask 1. The mask 1 is embodied inthe form of a plurality of mask regions 30. Each mask region 30 covers aregion of the semiconductor layer 2 that is separated by the subsequentetching process of the semiconductor chip. In the exemplary embodimentillustrated, the mask 1 has identical mask regions 30. Each mask region30 is embodied identically and has substantially a rectangular masklayer, in which 12 first openings 40 are introduced in each case. In theexemplary embodiment illustrated, in each case four first openings 40are arranged alongside one another, three rows of four first openings 40being provided. In each case two mask regions 30 are separated from oneanother by a second opening 41. The second openings 41 form aright-angled strip pattern. In each case two mask regions 30 are at asecond distance 14 from one another both in an x-axis and in a y-axis.The x-axis and the y-axis are perpendicular to one another and aredepicted schematically in FIG. 3. The first openings 40 have a firstdistance 13 in each case both in the x-direction and in the y-direction.What is achieved by the second openings 41 is that the semiconductorlayer 2 is severed between the mask regions 30 as a result of theformation of the separating trench during the etching process carriedout and explained with reference to FIG. 2, i.e. individualsemiconductor chips of the semiconductor layer 2 are separated.Moreover, through the first openings 40, corresponding pyramidal cutouts15 are introduced into the semiconductor layer 2, i.e. a central regionof the semiconductor chip is roughened. The central region is surroundedby a smooth, non-roughened region. In FIG. 3, a sectional linecorresponding to the sectional illustration in FIG. 1 is depicted byA-A.

Depending on the embodiment chosen, the mask 1 can also have a differentstructure, wherein the second distances 14 are chosen between adjacentmask regions in such a way that the semiconductor layer 2 is providedwith corresponding circumferential separating trenches 16 passingthrough the entire semiconductor layer 2 during the etching of thecoupling-out structure.

FIG. 4 shows a schematic illustration of a carrier 20, on which twosemiconductor chips 21 were structured from a semiconductor layer 2 inaccordance with the method described. Each semiconductor chip 21 has ona top side a central region 23 surrounded by an edge region 22. Thecentral region 23 has the coupling-out structure in the form of a cutout15, which were introduced into the top side of the semiconductor layer 2with the aid of the mask and the first openings 40. The central region23 is thus roughened. The edge region 22 was covered by acircumferential edge region of the etching mask of the second maskelement 12 during the etching process and is therefore not roughened.This has the effect that the smooth edge region 22 can be distinguishedoptically more easily from the roughened edge region 23. Consequently, asharp chip edge is identified optically, as a result of which an opticalinspection can easily be carried out automatically. An opticalinspection is necessary for example for checking for defects orcontaminants. Each semiconductor chip 21 is surrounded by acircumferential, etched edge region 24. The edge region 24 was etchedsimultaneously with the coupling-out structure.

Although the invention has been more specifically illustrated anddescribed in detail by means of the preferred exemplary embodiment,nevertheless the invention is not restricted by the examples disclosed,and other variations can be derived therefrom by the person skilled inthe art, without departing from the scope of protection of theinvention.

LIST OF REFERENCE SIGNS

-   1 Mask-   2 Semiconductor layer-   3 1^(st) semiconductor layer-   4 2^(nd) semiconductor layer-   5 Active zone-   10 1^(st) mask element-   12 2^(nd) mask element-   13 1^(st) distance-   14 2^(nd) distance-   15 Cutout-   16 Separating trench-   17 1^(st) boundary surface-   18 2^(nd) boundary surface-   20 Carrier-   21 Semiconductor chips-   22 Edge region-   23 Central region-   24 Edge region-   30 Mask region-   40 1^(st) opening-   40 2^(nd) opening-   42 Edge

The invention claimed is:
 1. An optoelectronic semiconductor chip,comprising: a semiconductor layer having an active zone for generatinglight; a coupling-out structure for coupling out light; a separatingtrench around a region of the semiconductor layer; and a circumferentialetched edge region, wherein the separating trench is introduced over theentire thickness of the semiconductor layer.
 2. The optoelectronicsemiconductor chip according to claim 1, wherein the coupling-outstructure is roughened and in a central region, and wherein the centralregion is surrounded by a non-roughened edge region.
 3. Theoptoelectronic semiconductor chip according to claim 1, wherein the topside of the semiconductor layer is provided with a coupling-outstructure by means of an etched surface.
 4. The optoelectronicsemiconductor chip according to claim 1, wherein the semiconductor layercomprises an epitaxially applied layer at least at the top side.
 5. Theoptoelectronic semiconductor chip according to claim 1, wherein thesemiconductor layer comprises at least one active layer on the basis ofInGaAlN.
 6. The optoelectronic semiconductor chip according to claim 1,wherein the semiconductor layer comprises at least one GaN layer.
 7. Theoptoelectronic semiconductor chip according to claim 1, wherein thecoupling out structure comprises cutouts in the semiconductor layer. 8.The optoelectronic semiconductor chip according to claim 7, wherein thecutouts have pyramidal depressions.
 9. The optoelectronic semiconductorchip according to claim 8, wherein the base of a pyramidal cutout has ahexagonal shape.
 10. An optoelectronic semiconductor chip, comprising: asemiconductor layer having an active zone for generating light; aroughened coupling-out structure in a central region for coupling outlight; a separating trench around a region of the semiconductor layer;and a circumferential etched edge region, wherein the central region issurrounded by a non-roughened edge region.